How to bind a module to an interface in testbench program block

SystemVerilog
1

blk_top.sv:

module blk_top;
  bit clk;
  test_module dut(
  .clk1                     (clk), 
  .clk2                     (clk)
  );
  
  // 200Mhz clock generator
  initial begin
    clk = 0;
    forever begin
        #(25) clk = ~clk;
    end
  end
  
  initial begin
    // Dump waves
    $fsdbDumpvars(0,blk_top);
  end
  
endmodule

blk_inf.sv:


interface test_module_if(
    input bit   clk_if
    );
    
    ...

endinterface: i2c_data_seq2_if

blk_run.sv:


program automatic blk_run;

    bind blk_top.dut test_module_if m_if(
        ...
    );
    
    `include "blk_env.sv"
    
    static blk_env env;
    
    initial begin
    
      env = new("my_env");
      
      uvm_resource_db#(virtual test_module_if)::set("my_env",
      "test_module_if", m_if);
      
      run_test();
    end
endprogram

Error:

Error-[SE] Syntax error
Following verilog source has syntax error :
“./blk_run.sv”, 4: token is ‘blk_top’
bind blk_top.dut test_module_if m_if(

How can I bind a dut module to an interface in testbench? What’s the problem?

2

In reply to yorkt:

after some example searching and attempts, I found out the correct way to assign a bind to virtual interface:


    bind blk_top.dut test_module_if m_if(
        ...
    );
program automatic blk_run;
 

 
    `include "blk_env.sv"
 
    static blk_env env;
 
    initial begin
 
      env = new("my_env");
 
      uvm_resource_db#(virtual test_module_if)::set("my_env",
      "test_module_if", blk_top.dut.m_if);
 
      run_test();
    end
endprogram

I think we need to put the bind declaration outside program block and need to add blk_top.dut. before m_if.
I don’t know the reason though.

3

I believe this is because m_if does not exist within blk_run, or blk_top, but rather you instantiated it within blk_top.dut, so it exists within blk_top.dut.

Binds instantiate a module in some other part of the hierarchy, not where they are declared.

4

The problem here is the program block does not allow any hierarchy, but
blk_top.dut test_module_if m_if(
…
);
represents a hierarchy.
This limitation makes the usage of program blocks in my eyes obsolete.

5

Ah, I can’t help there as I don’t use program blocks. I wouldn’t have expected to be able to instantiate structural elements (modules and interfaces) inside a program block, but it appears it can bind them and refer to ones instantiated elsewhere at least.

6

Do not use program blocks. Use a module instead. Are Program Blocks Necessary? - Verification Horizons