How to assign multidimensional array with default value in systemverilog

SystemVerilog
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1

I have a variable in class

rand int A[srting][int] = '{default : -1};

but tool says compile error : Assignment pattern element ‘-1’ : Cannot assign a packed type ‘bit signed[31:0]’ to an unpacked type ‘int $[int]’

I would like to assign default value to all array cell.

Either any string is not found, or any int is not found, the value shoule be -1.

What is the correct way to achieve it?

Thanks.

2

In reply to Jacky40210:

You need to specify the default for both dimensions:


rand int A[string][int] = '{default : '{default : -1}};
1 Like
3

In reply to cgales:

Hi cgales,

I know this assignment method, but I am wondering what the value would be if index string is found, but index int is not found？

For example, I just assign A[ABC][0] = 1, A[DEF][1] = 1

I hope that

A[ABC][1] = default value (index string found, but index int not found)
A[BCD][0] = default value (index string not found, but index int found)

will

rand int A[string][int] = '{default : '{default : -1}};

achieve this ?

I assume this implies that “if index string not found, and index int also not found, then the value will be -1”

Isn’t it?

Thanks

4

In reply to Jacky40210:

I would expect it to work that way, but you will need to test and verify. You will need to work with your tool vendor if you don’t get the expected results to determine the correct method.