How to assign inout port into the interface of Systemverilog?

SystemVerilog
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4

In reply to UVM_LOVE:

When you want to read the output from your DUT, you need to set the interface inout to 'z so that you aren’t conflicting with the DUT. Do you do that? Your code only shows setting it to 1’b1.

It would be beneficial to provide a complete example which shows your issue so that someone can provide a solution.