How to assign inout port into the interface of Systemverilog?

SystemVerilog
,
3

In reply to cgales:

Thanks reply cgales.
But even if I modified with

module my_dut (
      CMD,
      ...
);
 
  inout CMD;
  reg m_CMD;
  reg m_CMD_OE;
  assign CMD = m_CMD_OE ? m_CMD : 1'bz;
...
endmodule

Still does not work.

Originally, the code has been controlled as the below

module myTb;
import uvm_pkg::*;

reg clk, cmd;
wire m_cmd = cmd;
pullup i1(m_cmd);

//cmd control
cmd = 1;

my_dut u_dut(m_cmd, clk, ....)
...
endmodule

I changed it to the interface as the below.

interface my_if(
    inout wire w_my_command,
    ...
);
 
logic my_command = 'bz;
      assign w_my_command = my_command;
...
endinterface

Command send no problem working good but when it responds from DUT, command port goes to ‘x’.
Any clue please.