How to assign inout port into the interface of Systemverilog?

SystemVerilog
,
2

In reply to UVM_LOVE:

When using inout ports, you need to ensure that there is only one active driver at a time. Your my_dut is continuously driving CMD, which causes contention when your agent is attempting to drive it at the same time.

In my_dut, you should have an output enable to know when to drive:


module my_dut (
      CMD,
      ...
);
 
  inout CMD;
  reg m_CMD;
  reg m_CMD_OE;
  assign CMD = m_CMD_OE ? m_CMD : 1'bz;
...
endmodule