How to assign floating value to a real port?

SystemVerilog
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1

I have a real output port , where in some conditions the values is required to be floating ie Z .
Is there a way to support Z for real ports in SV ?

2

Read LRM 1800-2012 6.12 Real, shortreal, and realtime data types
Here in 6.12.2 conversion write that x or z convert to zero.
it means real type is not support x or z.
so i think you can not drive this on real data type.

3

In reply to prafulborad3@gmail.com:

Thanks Praful ,
Yes I aware the LRM doesnot allow to model the real ports as x/z . Cadence simulator support wreal ports as wrealx/ wrealz .

4

In reply to ruchi yadav:

You can create a wrapper module that has a 64-bit logic output port. Then you can use the $realtobits function to convert the real signal to a logic signal that can also be driven to 'z.