How to assign a single dimensional array to a port, which is multidimensional?

SystemVerilog
1

Hi All,

How to assign a single dimensional array to a port, which is multidimensional?

Let’s say I need to assign a wire A[2*W-1:0] to port B[W-1][W-1]. How can I do so? How could casting work here?

Thank you!

2

I am assuming you need a bit vector with W**2 bits and not 2*W bits. Also I assuming that W is a parameter. I would suggest using nested generate loops and assemble the 2 dimensional array signal.

3

In reply to dmitryl:

In addition to A should be W**2, the bit-stream operation will be an good option for you. You can try:


assign B = {>>W{A}};