How to assert a bit sequence using concurrent assertions

SystemVerilog
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3

In reply to raku:

1)Like what is the input the DUT.
2) What is the output from DUT.
if (reset_n && Enable)==1 output is 11010101

clock used for assertion is of time period of 1 bit with respect to data"
as the data is serial ,so one bit per clock, and i want to use same clock for assertions