How to add delay between two UVM Phase

UVM
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1

Hi Verification Academy Forum Desk,

As per the subject I’ve the following query. In my test I’m passing 2 different sequences, emif_sequence and image_sequence. emif_sequence is for configuring my system which is to be done first by the emif_driver and I’m doing it. After that the image_driver should start sending packet after getting the enable signal from the emif. But though the emif_driver is acting properly, but my image_driver is getting activated before the time, so I’m losing packet at the receiver side, because during that time receiver hasn’t receive the enable signal from the emif. So please tell me how to delay the operation of image_driver or how to add delay between two UVM phases, as my emif is running in pre_main_phase and image is inmain_phase. Following is my code sample.


class my_project_verif_test_4k_x_nk extends my_project_verif_test_base;
 
    my_project_verif_env env;
    my_project_verif_log log;
    bit is_timeout  = 1'b0;
    my_project_verif_env_cfg_ddr3_ctrl_mon_test env_cfg;
 
    `uvm_component_utils(my_project_verif_test_4k_x_nk)
 
    function new(string name = "my_project_verif_test_4k_x_nk",uvm_component parent=null);
      super.new(name,parent);
      log = new("NETRA_4K_X_nK_TEST");
      `spark_verif_note(log,"Inside constructor");
    endfunction : new
 
    virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);

    //Override Configuration
    env_cfg = new("test_env_cfg");
    uvm_config_db#(my_project_verif_env_config)::set(this,"*","env_cfg",this.env_cfg);

    // Set default sequence
    uvm_config_db #(uvm_object_wrapper)::set(this,"*.emif_gen.pre_main_phase",
                                     "default_sequence",
                                 my_project_verif_emif_std_sequence::type_id::get());
      // Set default sequence
    uvm_config_db#(uvm_object_wrapper)::set(this,"*.image_gen.main_phase",
                                       "default_sequence",
                                   my_project_verif_image_4k_x_3k_seq::type_id::get());
    endfunction : build_phase
 
  endclass : my_project_verif_test_4k_x_nk
2

You can try the method for communication between two precedure. As you wish, you can define an event in your env that two driver may use. If the emif_driver set enable, the event is triggered. Then the image_driver wait for the event.

3

While we don’t advocate the use of the config/main/… phases, we certainly think it’s a bad idea to use any of the pre_ or post_ variations of those. As I understand it, you want to execute the my_project_verif_emif_std_sequence first, followed by the my_project_verif_image_4k_x_3k_seq. That’s incredibly easy to do from your test in the run_phase, which is where stimuli like this should be handled. Using the default_sequence is unnecessarily cumbersome and can be confusing in some cases. Instead, simply do:


virtual task run_phase(uvm_phase phase);
  emif_seq = my_project_verif_emif_std_sequence::type_id::create("emif");
  image_seq = my_project_verif_image_4k_x_3k_seq::type_id::create("image");
  phase.raise_objection(this, "starting");
  emif_seq.start(emif_agent.sequencer);
  // optionally wait for an event indicating enable signal received
  image_seq.start(image_agent.sequencer);
endtask

This gives you much more control over the interactions of the two sequences, without mucking with the pre/main phases and without having to worry about default_sequences, which could unknowingly get overridden or lead to other problems.
Good luck,
-Tom