How to add a timing window to a SV sequence

SystemVerilog
,
1

Hi all,

I am trying to write a systemverilog sequence describing this behaviour:

  • wake Signal is by Default Zero
  • we are interested to see 2 consecutive pulses on wake . this is called wake pattern.
  • a valid pulse : when wake goes 0 → 1 it must remain high for min 0.5 us and max 3us
  • there will be a wake = 0 between 2 high pulses
  • at the end of second valid pulse wake is completed.
  • a complete wake must happen in this window: min 0.5 MS max 10ms
    this means : a valid pulse + wake = 0 + second valid pulse

I have written the needed sequence to detect a valid pulse. It is called wake_dom . I use the wake_dom sequence in another sequence called wake_pattern as you see below :

sequence wake_dom;
	    @(posedge clk_80mhz_i)
        !ad_wk_i ##1 
        seq_repetition_range(ad_wk_i,wk_dur_min,wk_dur_max)##1
       !ad_wk_i;
   endsequence   


 sequence wake_pattern;
	 @(posedge clk_80mhz_i)	
	 wake_dom ##[0:800000] (wake_dom and (cnt == 1));
 endsequence

Can anyone help me to add the complete wake window requirement to the sequence wake_pattern
currently the wake_pattern sequence is not supporting this requirement.
the window is [0.5ms : 10ms]

many thanks
Mohammed