How to access Register/memory via backdoor path?

UVM
1

Hi ,

I have a UVM register package which include a memory like this:

class ICTMACT extends uvm_mem;
`uvm_object_utils(ICTMACT)

  function new(string name = "ICTMACT");
    super.new(name, 128, 32);  //depth=128 , width =32
  endfunction

endclass

This memory was added in uvm_reg_block class
class reg_block extends uvm_reg_block;
…
ICTMACT ICTMACT_mem;
ICTMACT_mem = ICTMACT::type_id::create(“ICTMACT_mem”, , get_full_name());
ICTMACT_mem.configure(this,null,“cts_top_inst…dist_ram_inst.ram_data[128]”); //line 3971
…
endclass

in my testcase ,I use this code to access memory via backdoor
reg_block_inst.write_mem_by_name(status,“ICTMACT_mem”,'h0,'h11223344,UVM_BACKDOOR);

I gave the memory a backdoor path: “cts_top_inst…dist_ram_inst.ram_data” ,this path point to a distribute ram, in this ram primitive ,there is a memory named ram_data
reg [31 : 0] ram_data [127 : 0];

when running simulation ,there is a error happened :

** Error: …/register/cri_pkg_uvm.sv(3971): Number of actuals and formals does not match in function call.

what is wrong with it , how can I specify the backdoor path of memory? if you have some idea ,please give me some suggestion or example of memory backdoor access.

thank you!

Best Regards : Adams