How to access or best way to access verilog module task in UVM test

UVM
,
1

Hi,
how to access or best way to access the verilog module task in UVM test?



module top;
//
task read_task(arguments: ID, ADDR, DATA);
task write_task(arguments: ID ADDR, DATA);

endmodule



class my_test extends uvm_test;
top top_inst; ?

task run_phase(uvm_phase phase);

//
top_inst.read_task(); ??
endtask


endtest
2

In reply to muku_383:

Here are some ideas: Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy