First of all, you should be using run_phase() and not main_phase().
Second of all, why would you possibly want to hard-code a hierarchical path to the DUT in your UVM? You are completely sacrificing the ability to reuse anything when you do that. Instead, you should create an interface that includes the signal(s) you want to access (the interface could include the hierarchical reference), and then you could pass that interface as a virtual interface via the config_db to your test/env and access it that way.
Good luck,
-Tom