How the within syntax is working in SVA

SystemVerilog
, ,
6

In reply to ben@SystemVerilog.us:

Hi Ben,
What is the problem without antecedent?
It seems this property can work.
Thank you

property Better_but_still_BAD_xyz; // No antecedent
    @(posedge clk);
    ($fell(a) ##[1:$] $rose(b)) within 
       ($rose(a)[->1] ##[1:$] $rose(c));
endproperty