How the within syntax is working in SVA

SystemVerilog
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2

In reply to noha shaarawy:

Your property is checking at every clock edge that ‘a’ fells probably you want this

property xyz;
@(posedge clk)
$fell(a) |-> ##[1:$] $rose(b) within ($rose(a) ##[1:$] $rose(c));
endproperty

I need to simulate an example but it think this means when a fells b should go high at some point within the sequence a followed by c.

HTH,
-R