How should asynchronous reset be modeled?

SystemVerilog
, , , ,
1

Hi,
I am writing some behavioral model (example is shown below).
How should asynchronous reset be modeled?


interface some_if(input clk1, input clk2);
  bit[7:0]  data;
  bit       rst1;
  
  clocking cb_clk1 @(posedge clk1);
    default input #1step output #2ns;
    input   i_data = data;
    output  o_data = data;
  endclocking
  
  clocking cb_clk2 @(posedge clk2);
    default input #1step output #2ns;
    input   i_rst1 = rst1;
    output  o_rst1 = rst1;
  endclocking
  
  class t_some_if extends t_base_some_if;
    task wait_for_clk1;
      @cb_clk1;
    endtask
    
    function bit[7:0] get_data();
      return cb_clk1.i_data;
    endtask
    
    task set_data(bit[7:0] data);
      cb_clk1.o_data  =  data;
    endtask
    
    task wait_for_clk2;
      @cb_clk2;
    endtask
    
    function bit get_rst1();
      return cb_clk2.i_rst1;
    endtask
    
    task set_rst1(bit rst1);
      cb_clk2.o_rst1  =  rst1;
    endtask
    ...
  endclass
endinterface

class some_module1;
  t_base_some_if m_some_if;

  task run1();
    forever begin
      m_some_if.wait_for_clk1(); //here I want clear data on asynchronous reset
      ...
      m_some_if.set_data(data);
      ...
    end
  endtask
endclass

class some_module2;
  t_base_some_if m_some_if;
  task run2();
    forever begin
      m_some_if.wait_for_clk2();
      ...
      m_some_if.set_rst1(1);
      ...
      m_some_if.set_rst1(0);
      ...
    end
  endtask
endclass

I think, asynchronous reset could be modeled using fork… join_any (example shown below).

interface some_if(input clk1, input clk2);
  ...
  bit       rst1;
  
  class t_some_if extends t_base_some_if;
    ...
    task wait_for_rst1;
      @(negedge rst1);
    endtask
    
    function bit get_rst1();
      return cb_clk2.i_rst1;
    endtask
    ...
  endclass
endinterface

class some_module1;
  t_base_some_if m_some_if;

  task run1();
    forever begin
      fork
        m_some_if.wait_for_clk1();
        m_some_if.wait_for_rst1();
      join_any
      disable fork;
      if(m_some_if.get_rst1() == 0) begin
        m_some_if.set_data('0);
      end
      else begin
        ...
        m_some_if.set_data(data);
        ...
      end
    end
  endtask
endclass

Also I think asynchronous reset could be modeled using mailbox.
What way do you recommend?