assign overflow = (sig_4_bits + sig_1_bit > 4'hF) ? 1'b1 : 1'b0;
If sig_4_bits is 4’hF, while sig_1_bit is 1’b1, how will the relational operator evaluate it?
In general, what is the rule for relational operators on dealing with bit sizes?
In reply to Reuben:
Referring to LRM:
The number of bits of an expression is determined by the operands and the context. Casting can be used to set the size context of an intermediate value.
SystemVerilog uses the bit length of the operands to determine how many bits to use while evaluating an expression.
From an example in LRM, in the case of the addition, the bit length of the largest operand, including the left-hand side of an assignment, shall be used.
logic [15:0] a, b; // 16-bit variables
logic [15:0] sumA; // 16-bit variable
logic [16:0] sumB; // 17-bit variable
sumA = a + b; // expression evaluates using 16 bits
sumB = a + b; // expression evaluates using 17 bits
Also the relational operator uses same rule:
// Section 11.6 from LRM:
i ? j : k max(L(j),L(k)) i is self-determined
In the current case, if the largest bit length is 4-bits, then the expression is evaluated to be of 4-bits. Of overflow or any other variable is more than 4-bits, then that bit length is used.
assign overflow = (sig_4_bits + sig_1_bit > 4'hF) ? 1'b1 : 1'b0;
// assuming $bits(sig_4_bits) = 4 and $bits(sig_1_bit) = 1. overflow = 0 since max size of following expression will be 4 bits
//
// expression: (sig_4_bits + sig_1_bit > 4'hF)
//
Here, the comparison expression will be determined with size of sig_4_bit and sig_1_bit variables. And not the overflow bit.
Refer to System Verilog LRM 1800-2012, Chapter 11 and Evaluating expressions post for more information.