How programe block remove race condition

SystemVerilog
,
1

Hi,

Clocking block always provide #1step delay(Skew) and that’s enough to remove race condition. I read that when multiple clocking block will us, then programme block will remove race condition becouse it works in different region(Reactive region).

Confusion : I have declare two clocking block and LHS of 1st Clockingblock is RHS of 2nd Clockingblock, In testbench it will create race condition .
How program block will remove this race condition as it will sample both the signal at same region(Reactive region).

Regards,
Upendra

2

You are correct. Program blocks do not remove all race conditions and are not recommended to use. See Are Program Blocks Necessary? - Verification Horizons

3

In reply to dave_59:

Thanks Dave, for quick and helpful reply .If you have any waveform with respect to simulator regions then please share with me. So i can understand all the regions , if its not available then not a problem.

Regards,
Upendra