I am done with basic coding using python. I searched a lot to find python scripting useful for the VLSI domain, but couldn’t find proper stuff. Everyone suggests that’s is used for regressing test cases. But how in particular is it done, and is any DPI used to link python to UVM. How is python used as a scripting language for Verification purposes in real-time? What are the sources to learn the python scripting? Could you please provide links or materials or books. Thank you in advance
In reply to Verif@dj:
I’v e seen Python used for two distinct tasks in verification.
\The first is in scripting around the invocation of your simulation tests, and groups of simulation tests forming your regressions. People do this in place of Makefiles, or integrated with them. If you looking for job security, this might be the way to go :)
The other is in the actual generation of stimulus, linked in through the DPI/PLI. My bigoted point of view will say that this only works up to a certain level of complexity. As an interpreted language, you’ll never get the same level of performance as a compiled language.
You might want to search the dvcon.org archives for papers on this subject.
Python is a general-purpose programming language that can do many things, like any other language such as C++, Java, etc. It is interpreted for the most part, but the performance degradation is not likely an issue if you use it for automating and managing various design and verification tasks and flows, such as test/regression management (sim, formal/static, emulation), coverage/data analysis (machine learning opportunity), etc.
If you want to actually use Python as a substitute for SystemVerilog and UVM - that is to model the testbench and verification components - there is CocoTB (GitHub - cocotb/cocotb: cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python). Why might you want to do this? I know of an application in FinTech where this is used for FPGA verification in geographical locations where traditional design verification engineers with skills in SystemVerilog and/or UVM are hard to find. This would be an area where you might realize stimulus generation in Python. Personally, I think you would be better off keeping it in SystemVerilog, especially since you have the constraint solver at your disposal rather than making your own or hunting for one in the open-source community.
If you want to continue learning Python, you can find a plethora of resources just a Google search away. The documentation in https://www.python.org/ is a good starting point and reference. If you have a question about something specific, you can find a lot of good info in Stack Overflow (https://stackoverflow.com/). There are so many resources for Python, perhaps now the most popular language worldwide, that you might as well just start searching and figuring out your own learning path.
Thank you dave_59 for the valuable information as it cleared a lot of doubts I had.