How does Synthesis of D Flip FLop differs if it is coded using Blocking assignment and Non Blocking assignment

SystemVerilog
,
4

As Dave mentioned, in this case there is no difference in the synthesis result. But for the below code the implementation will change.

##Blocking Assignment 
always @(posedge clk or negedge rst) begin
     if(!rst) begin
          a = 0;
          b = 0;
     end else begin
          a = d;
          b = a;
     end
end

##Non-Blocking Assignment
always @(posedge clk or negedge rst) begin
     if(!rst) begin
          a <= 0;
          b <= 0;
     end else begin
          a <= d;
          b <= a;
     end
end

BLocking assignment code will have only single flop while nonblocking assignment will have two flops.