How does string type to bit type convert in System Verilog?

SystemVerilog
,
1

I have a question about how does SV do type conversion between string and bit? Especially for “*”, “.”, “0”.
Why EDA tool not even throw a warning for assigning a bit with string type?

module tb;
  bit a="*";
  string b="*";
  bit c="0";
  bit d=".";

  initial $display(a,,b,,c,,d);
endmodule

The output is:
0 * 0 0

#-------------------------#
string → bit

  •   ->     0

. → 0
0 → 0
#--------------------------#

2

In reply to mlsxdx:
Due to backward compatibility with Verilog, what looks like a string literal in quotes is really a numeric literal. Verilog treats a string literal as a multiple of 8-bits vector based on the number of characters in the string literal. An unfortunately, assigning an 8-bit integral value to a single bit integral type is perfectly legal and will silently truncate.