How does simulator treat a 1->x, 0->x, x->1, 0->1 transition?

SystemVerilog
,
1

Hi,

Interested to know how the simulator would treat the below signal state transitions:

1->x
0->x
x->0
x->1

Whether they will be treated as negedge/posedge in the design logic?

Please guide. Not sure if different simulators have a different behavior for this or it’s universal rule supported by all simulators.

Thanks,
Sandhya

2

In reply to Sandhya Krishnan:

Hi,
Interested to know how the simulator would treat the below signal state transitions:
1->x
0->x
x->0
x->1
Whether they will be treated as negedge/posedge in the design logic?
Please guide. Not sure if different simulators have a different behavior for this or it’s universal rule supported by all simulators.
Thanks,
Sandhya

Hi,

The 2017 LRM Section 9.4.2 Event control provides with a table that describes what are the transitions.

“— A negedge shall be detected on the transition from 1 to x, z, or 0, and from x or z to 0
— A posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1”

Now this forum is not intended to discuss tool specific issues, if you are seeing something different to the LRM please contact your Tool provider or check your user manual for more information.

HTH,
-R