How do you determine if a signal is synchronous to a particular clock?

SystemVerilog
1

What is the SVA code to determine if a signal or bus is synchronous to a clock?

2

In reply to VerifEx:

SVA already assumes the signals you specify are synchronous to a clock. You need a clock domain crossing (CDC) tool to help you with that. See https://verificationacademy.com/courses/clock-domain-crossing-verification