Hi Now I’m trying to studying the UVM.
In especially, “Transaction Adapter” currently I’m trying to understand it.
But I come across some query when I’m looking the below code.
As you can see the below code, it’s not completed code. so I’d like to modify the code.
Question. When I see “apb_transfer transfer;” the below code, I’m curious where “apb_transfer” does come from.
Because to use member variable of apb_transfer, I need to what member variables are declared.
But It’s not declared in this code so it’s too hard to know. From here I want to know that if you see the code to analysis and implement, then how do you usually do to analysis the UVM code?
class reg_to_apb_adapter extends uvm_reg_adapter;
`uvm_object_utils(reg_to_apb_adapter)
function new(string name="reg_to_apb_adapter");
super.new(name);
endfunction : new
function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
apb_transfer transfer;
transfer = apb_transfer::type_id::create("transfer");
transfer.addr = rw.addr;
transfer.data = rw.data;
transfer.direction = (rw.kind == UVM_READ) ? APB_READ : APB_WRITE;
return (transfer);
endfunction : reg2bus
function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
apb_transfer transfer;
if (!$cast(transfer, bus_item)) begin
`uvm_fatal("NOT_REG_TYPE",
"Provided bus_item is not of the correct type. Expecting apb_transfer")
return;
end
// UVM_REG
// LAB2A
// finish bus2reg function
endfunction : bus2reg
endclass : reg_to_apb_adapter