How do we write assertion for valid to be high while ready is low for AXi protocol

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Thanks Ben for quick reply. i was looking for only checking valid to be high while ready is low. once ready goes high in any cycle, valid has to be high and master can drive valid low in that cycle but assertion will capture that in next clock cycle. So, throught assertion is good for me.

between what will be assertion if i want the assertion to be passed irrespective of valid value when ready goes high. in the above assertion, one expect valid should be low and other expect valid to be high to make the assertion pass.

Thanks.