In reply to ben@SystemVerilog.us:
// A caveat on the use of that **throughout**
// The construct exp throughout seq is an abbreviation for the following:
(exp) [*0:$] intersect seq
// Your requirements: Once valid goes high on any channel, valid to be high
// while ready is low. You did not specify what the value of valid is when ready==1.
// The valid throughout ready[->1];
// means that when ready==1, valid==1
// If you need to specify that valid==0 when ready==1
// then you need to use the intersect of 2 sequences.
$rose(valid) |-> valid throughout ready[->1]);
ap_i1: assert property(@ (posedge clk) $rose(valid) |-> !valid[->1] intersect ready[->1]);
ap_thru1: assert property(@ (posedge clk) $rose(valid) |-> valid throughout ready[->1]);
http://SystemVerilog.us/vf/thruo_intersect.sv // testbench
http://SystemVerilog.us/vf/intersect.png // simulation
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
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- SVA in a UVM Class-based Environment
https://verificationacademy.com/verification-horizons/february-2013-volume-9-issue-1/SVA-in-a-UVM-Class-based-Environment