How do I use set_inst_override_by_type to an instance whose class has many children?

UVM
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1

I have a scenario where I want to override specific instance of base class with it’s extended class.
code for class and hierarchy :

class basechain extends uvm_component;

`uvm_component_utils(basechain) 

function new(string name = "basechain", uvm_component parent = null);
  super.new(name, parent);
endfunction   

// Constructor function
function initialize_setup (int size = 1);
   begin
      /* Some variables initialization here*/
   end
endfunction 


class extentedclass1 extends basechain;

`uvm_component_utils(extentedclass1)
function new(string name = "extentedclass1", uvm_component parent = null);
  super.new(name, parent);
  endfunction


function initialize_setup (int size = 1);
   begin
      
      super.initialize_setup(1);
endfunction



class extentedclass2 extends extentedclass1;

basechain DUTTop;
basechain DUTBot;


`uvm_component_utils(extentedclass2)
function new(string name = "extentedclass2", uvm_component parent = null);
  super.new(name, parent);
  endfunction  

function initialize_setup ();
   begin
      // Since we integrate other chains, set ours to 1
      super.initialize_setup(20);
  
      DUTTop = basechain::type_id::create("DUTTop",this);
      DUTTop.initialize_setup(2);
      DUTBot = basechain::type_id::create("DUTBot",this);
      DUTBot.initialize_setup(3); 
      
      
      
   end
endfunction

endclass


class dut_scanchains extends uvm_component;

`uvm_component_utils(dut_scanchains) 
function new(string name = "dut_scanchains", uvm_component parent = null);
  super.new(name, parent);
    endfunction 

basechain integexp;

task scanchain_setup(dut_scanchain_type scanchain_type);

         integexp=basechain::type_id::create("integexp",this);
         integexp.initialize_setup();
endtask                  

endclass

scanchain_setup function is called in build phase of one the class
Working Topology:


--------------------------------------------------------------------
Name                         Type                        Size  Value
--------------------------------------------------------------------
uvm_test_top                 dut_level0_integchain       -     @344 
  m_env                      dut_env                     -     @375 
    m_agent                  dut_agent                   -     @773 
      m_driver               dut_driver                  -     @792 
        bdbfm                dut_bd_bfm                  -     @990 
        bfm                  dut_bfm                     -     @981 
        rsp_port             uvm_analysis_port           -     @811 
        seq_item_port        uvm_seq_item_pull_port      -     @801 
        tbbfm                dut_tb_bfm                  -     @999 
      m_monitor              dut_monitor                 -     @958 
        item_collected_port  uvm_analysis_port           -     @967 
      m_sequencer            dut_sequencer               -     @821 
        rsp_export           uvm_analysis_export         -     @830 
        seq_item_export      uvm_seq_item_pull_imp       -     @948 
        arbitration_queue    array                       0     -    
        lock_queue           array                       0     -    
        num_last_reqs        integral                    32    'd1  
        num_last_rsps        integral                    32    'd1  
    m_scoreboard             dut_scoreboard              -     @782 
      packets_collected      uvm_tlm_analysis_fifo #(T)  -     @1017
        analysis_export      uvm_analysis_imp            -     @1066
        get_ap               uvm_analysis_port           -     @1056
        get_peek_export      uvm_get_peek_imp            -     @1036
        put_ap               uvm_analysis_port           -     @1046
        put_export           uvm_put_imp                 -     @1026
      dut_checker            dut_chk                     -     @1080
  m_dutscanchains            dut_scanchains              -     @362 
    integexp                 extentedclass2              -     @399 
      Block0                 basechain                   -     @606 
      DUTBot                 basechain                   -     @597 
      DUTTop                 basechain                   -     @588 
     
--------------------------------------------------------------------

Now I make the following changes:

extentedclass2 integexp;

to

basechain integexp;

basechain is the parent. I wish to override this basechain instance with specific extentedclass2 type based my test requirement. I used

set_inst_override_by_type("m_allchains.integexp",basechain::get_type(), extentedclass2::get_type());

Instance overriding seem to be successful but I don’t see sub instance appearing. subchains of base class and other instances are missing (compare the working topology and non-working topology)
Example failing topology :


--------------------------------------------------------------------
Name                         Type                        Size  Value
--------------------------------------------------------------------
uvm_test_top                 dut_level0_integchain       -     @344 
  m_env                      dut_env                     -     @375 
    m_agent                  dut_agent                   -     @413 
      m_driver               dut_driver                  -     @432 
        bdbfm                dut_bd_bfm                  -     @630 
        bfm                  dut_bfm                     -     @621 
        rsp_port             uvm_analysis_port           -     @451 
        seq_item_port        uvm_seq_item_pull_port      -     @441 
        tbbfm                dut_tb_bfm                  -     @639 
      m_monitor              dut_monitor                 -     @598 
        item_collected_port  uvm_analysis_port           -     @607 
      m_sequencer            dut_sequencer               -     @461 
        rsp_export           uvm_analysis_export         -     @470 
        seq_item_export      uvm_seq_item_pull_imp       -     @588 
        arbitration_queue    array                       0     -    
        lock_queue           array                       0     -    
        num_last_reqs        integral                    32    'd1  
        num_last_rsps        integral                    32    'd1  
    m_scoreboard             dut_scoreboard              -     @422 
      packets_collected      uvm_tlm_analysis_fifo #(T)  -     @657 
        analysis_export      uvm_analysis_imp            -     @706 
        get_ap               uvm_analysis_port           -     @696 
        get_peek_export      uvm_get_peek_imp            -     @676 
        put_ap               uvm_analysis_port           -     @686 
        put_export           uvm_put_imp                 -     @666 
      dut_checker            dut_chk                     -     @720 
  m_dutscanchains            dut_scanchains              -     @362 
    integexp                 extentedclass2              -     @399  
--------------------------------------------------------------------

Clearly underlying instances are missing and They are not being instantiated. What am I doing wrong ?

2

The parent and child relationship should only apply to the topology of the environment. When discussing inheritance, you should use the terms base class and extended class. This differentiation can significantly help when describing your issue.

From your post, it looks like common_chain is your base class, and dut_Integ_chain is an extended class. Is this correct?

The first topology you posted shows variable ‘integexp’ of type ‘dut_Integ_chain’ under ‘m_dutallchains’.

You state that you redefine ‘integexp’ of type ‘dut_Integ_Scanchain’ to ‘common_chain’. This doesn’t match the above topology (‘dut_Integ_chain vs. dut_Integ_Scanchain’), so it is not clear what you are changing. Is ‘dut_Integ_Scanchain’ also an extended class of class ‘common_chain’?

You then try to override the instance ‘m_allchains.integexp’, which doesn’t match any instance in the first topology you posted (‘m_dutallchains.integexp’ seems to be the closest). Also, the second topology posted shows ‘m_dutscanchains.integexp’, which is even more confusing.

It seems like you are mixing several environments based on the different instance names and hierarchies which makes determining your issue very difficult. Can you restate your issue using a consistent example so we can provide further assistance?

3

In reply to cgales:

I have updated the details and problem description. Do you see anything unusual in the code ?

4

In reply to Varunshivashankar:

Several things to help:

  1. You should make use of configuration objects and the build_phase to be more suitable for UVM. This precludes the need to create specialized setup and initialization functions and is more in line with UVM recommendations. All components should be created and configured in the build_phase.

  2. The initialize_setup() functions don’t have a return type. The function should be declared as void if you don’t need a return value.

  3. The initialize_setup() function needs to be declared as virtual. This will allow the proper use of the override functionality.

5

In reply to cgales:

Thanks. Making the function Virtual and void solved the problem.