How do I implement a MOVE operation using in SystemVerilog? Is it same as move assignment operator in C++? Where can I find an example code?

I have been asked this and I have searched everywhere but I never got any code on SystemVerilog.

How do I implement a MOVE operation using in SystemVerilog? Is it same as move assignment operator in C++? Where can I find an example code?

It has something to do with polymorphism I assume.

In reply to abhilash1106:

There is no built-in MOVE operator in SystemVerilog, but you can easily add a move() method to any class, or create a parameterized static method’

virtual class move#(type T);
 static function T to(inout T from);
    to = from;
    from = null;
 endfunction
endclass

anyclass A, B;

initial begin
          A = new();
          B = move#(anyclass)::to(A);
          ...