In reply to dave_59:
Hi Dave, could you look into my question here please: Simulate OpenDrain line | Verification Academy
I read your paper but I haven’t found much usefull in my situation. I think it is due to the fact I am trying to simulate Xilinx’ IOB, so that means I don’t have the I/O/T signals, I therefore only have the inout port from the IOB… so as far as I know I can’t do anything like:
assign sig = T ? 'z : O;