Simulate OpenDrain line

SystemVerilog
, , ,
1

Hello,

I am having a lot of trouble trying to simulate an OpenCollector line.

Basically I have a design with a Xilinx’ IOB driver which is supposed to connect to an OpenDrain line. My goal is to have multiple modules all connected to the same line (which should also have a pullup) so that when one modules pulls the line low all other modules can see it. Ideally I would also like to model collisions, in other words, if more than one module drive the lines in a Push&Pull fashion (the behaviour of the IOB is configurable) I would like to see that in the simulation with an X or U.

Moreover, I would also like to model delays. In other words, I would like to be able to model how long it takes for the signal to propagate from one port to another.

What does SV offer for this purposes?

Thanks!

2

In reply to arquer:

To try to elaborat further:

  1. I have a module which acts like a “hub” to give it a name. In my mind this modules is the one who would physically have the OpenDrain line with it’s pullup resistor.
  2. This “hub” has N SystemVerilog Interfaces, and a “logic” signal which is the OpenDrain physical line.
  3. I have N modules with an inout port (with an IOB instantiated) which is supposed to be connected to the OpenDrain line.
  4. I want to place a pullup resistor on the OpenDrain line (located inside the “hub” modules) and I also want to connect all the ports from the N modules together.

Inside the Hub modules I could do:

pullup i_pullup(oc_line);

However, how do I also connect all the N modules together with each other and with that OC line?

Thanks.