In reply to Naven8:
The problem is that the statement
inf.w1 <= 1'b1;
is a non-blocking procedural assignment to a wire, it is not a continuous driver to the wire. A procedural assignment has no duration to it; you are depositing the value of the expression on the RHS of the ‘<=’ to the variable on the LHS. The variable stores the value until there is another procedural assignment that replaces the old value with a new one. The execution of the procedural assignment is part of a sequential thread of procedural statements that usually starts with an initial or always block construct.
A continuous assignment
assign w1 = w2;
is structural, not procedural. You are driving the value of the expression on the RHS to the net on the LHS, for all time. A change at anytime on the RHS expression cause a new value to be driven on the LHS.
It seems that VCS allows procedural assignments to wires, and that seems to work as long as there are no other continuous assignments to the wire. In that case, you treat the wire the same as you would a variable. The problem comes in when you try to mix the two kinds of assignments. Let’s say the DUT is continuously driving a 1’b1, and the testbench makes a procedural assignment to 1’b0. Does the procedural assignment replace the value being driven with 1’b0, like any other procedural assignment. Or does it try to do wire resolution and make the wire go to 1’bx. I suppose the LRM could define an answer for this, but Verilog was designed as a description language to show more intent. As an analogy, you could define an array with fixed size 10 elements and allow the 11th element to be assigned by growing the array by one element when that happens, but then what was the point of declaring a 10 element array in the first place?