How Data gets updated to register model during auto-predict = 1 ? Confused how/who updates it!

UVM
1

Hello Folks,

Had a strange confusion with respect to uvm register model with auto_predict = 1 and doing register based write/read.

a. With autopredict=1, when we do register write using register sequence. the register transactions i.e. addrs, data is copied into bus sequence item and that is driven by the bus sequencer-driver to the DUT. If autopredict = 0, then monitor capture the data and asks the user defined predictor to update the register model. Whereas if we use the autopredict=1, who updates the data ?

b. Similarly for read, with autopredict=1, the register transaction is copied to bus transaction in the adapter and the driver generates the addrs for read. But I see/read that read data is updated in the register model before read is done. Now, what value/how is it getting updated in the register model?

Please clear the crazy doubt out of my mind ! Thanks in advance.

Desperado :-)

2

In reply to desperadorocks:

What do you mean by “before read is done”?

The way it should work is:

  1. Register model calls adapter
  2. Adapter converts reg item to bus item
  3. Bus item is started on bus sequencer and sent to bus driver
  4. Bus driver drives signals according to protocol (write, address, etc.)
  5. Bus driver collects response and passes it up
  6. Register model uses response for update

By “bus driver collects response” I mean, for example, collecting the read data in case of read operation. This can be done in two ways. The easiest way is for the driver to update the ‘data’ field inside the item it got from the sequencer. The more complicated way is to send a separate response object. If this is the case, the adapter has to know this, by setting its ‘provides_responses’ field.

Depending on which one you have implemented, make sure that the driver properly sends back the response information.

3

In reply to Tudor Timi:

Hello Tudor,

Thanks for your response. So in the auto_predict mode, if the driver doesn’t send the response back, then the adapter will fill up the register model with some random data which was previously present in the sequence item ? Correct me if my understanding is wrong ?

What if we are using the default register bit-bash sequence available with the uvm library to check the register model ? Does those default bit bash sequence gets the response back from our assigned driver ?

Please clarify my above queries.
Thanks !

4

In reply to desperadorocks:

For question 1, I guess yes, because you probably randomize some ‘data’ field even when you do a read and that field isn’t used for driving. This is easy to check.

For question 2, I’ve never used these bit-bash sequences, but I don’t think the question is valid. This whole update mechanism should work regardless of what sequence you’re running.

5

In reply to Tudor Timi:

Thanks Tudor for your inputs… Actually didn’t provide the provides_response bit and that actually skipped the response which I was sending from the driver. Well it worked now and your inputs helped. Appreciate your timely help.

Desperado !