How could i simulate systemc code in questasim using command qverilog

SystemVerilog
1

Hi all,
I need following detail to compile
systemC code in questasim using Single Step Command Like(qverilog)

Is there any particular switches for compile & Simulating systemC codes....

Eg: In Cadence they provide some swiches like -sysc under irun…

if any body know tricks to overcome this Issue…

Note: If I add -ccflags “” it only understand *.cpp(C++) file…

Thanks,
Selvavinayakam.na

2

This exact question was just asked yesterday. https://forum.verificationacademy.com/forum/verification-methodology-discussion-forum/systemverilog-and-other-languages-forum

3

In reply to dave_59:

Thanks Dave for reply,

I referred Questa User Manual, til now i am not getting any idea about that,
If u have any example reference file, please share…
my task is to call system_verilog DPI-C Function from system_C Function…

.sv<----DPI---->.cpp[software_side]<------>*.cpp[system_c Function]…

Thanks,
Selvavinayakam.na

4

In reply to selvavinayakam.na:

In the /examples/sysyemc directory, there are various examples on how to compile systemc code with sccom.

The SystemVerilog standard only supports a DPI-C to interface with straight C code. You can call an SV function from SC, but only with basic C types. Questa supports a DPI-SC extension. You can see an example in examples/systemc/systemc_dpi.