How can you get an assertion pass and fail in the same time slot?

SystemVerilog
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1

Found this question in Program block blog asked by Dave.
Quick quiz: How can you get an assertion pass and fail in the same time slot?
assertion result is known in reactive region as per system verilog event scheduling.

so if the assertion is written in program block then will it sample and evaluate and give pass/fail result in reactive region?

2

In reply to to_learn_uvm:

[quote] assertion result is known in reactive region as per system verilog event scheduling.

But all signals are sampled in the Preponed region, just prior to the clocking event.
Since the assertion is based on those already sampled values, I don’t see how the region of the evaluation makes a difference. See my post
https://verificationacademy.com/forums/systemverilog/sva-evaluation
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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