How can i use "set_type_override_by_type" inside the register adapter

UVM
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1

Dear Academy,

I would like to change the type of my sequence_item/transaction inside the adapter.
I have tried to use in my environent


set_type_override_by_type ( uvm_object_wrapper original_type, 
                            uvm_object_wrapper override_type, 
                            bit replace=1);

however, because the adapter is an uvm object which does not have a component handler (at least i have not found), the create method cannot find the correct context and do the override. So it does not work.

Normally, the context is provided using this as below in the create function


seq_item_0 = exampletype::type_id::create("seq_item_0",this);

The register adapter is inside the uvm component “register predictor” as it is correct way of doing as explained in the academy. I cannot use “this” in create.

How can i do this?, How can i change the type of the sequence items inside the register adapter?
Best regards,

2

In reply to JA:

The creation of your object as you shawed it is wrong:

seq_item_0 = exampletype::type_id::create("seq_item_0",this);

It should be

seq_item_0 = exampletype::type_id::create("seq_item_0");

because an object does not belong to the testbench hierarchy and it does not have a parent.
In the adapter you have 2 things which are specific:
(1) The sequence
(2) the content of bus2reg and reg2bus

you can set the sequence, but you have to implement different functions bus2reg and reg2bus whan changing the sequence and the seq_item.
Inside the adapter there you need a if/else construct to set the correct functions.
Where is the benefit of using the override for the adapter?

3

In reply to chr_sue:

Hi,
I know that i cannot use

seq_item_0 = exampletype::type_id::create("seq_item_0",this);

That is what i have tried to say in my message. That is the reason why the “set_type_override_by_type” does not work. (without specifying the context the override in create does not work)
I want to use the override for the same reasons we use “set_type_override_by_type” in uvm components. i have a base sequence item and i want to specialize that sequence item. The specialized sequence item has some methods i would like to use in the adapter (in bus2reg, reg2bus functions). Obviously, i can avoid the problem implementing again these methods i need using the base class, but that is exactly what i want to avoid/spare. (Besides, the derived class can have new static parameters/generics that are important for the bus2reg/reg2bus)

The question is if i can use e.g. something like

seq_item_0 = exampletype::type_id::create("seq_item_0",.cntx("correctcontext"));

I would like that somehow the “create” find the factory reconfiguration for that xfer (sequence item) in the adapter. Using “cntx” with the correct path would be an idea. Is it possible to make the “set_type_override_by_type” work inside the adapter?

4

In reply to JA:

I’m assuming you want to set an override for creation in a particular register adapter, and there are other places where the same exampletype is being created that you do not want overriden. In that case you need to use by_instance overrides, not by_type.

The context is just a string; it does not have to be a real uvm_component path. As long as you can give the register adapter a unique name, you can use that name as the context for setting the override and providing it when creating the object.

5

In reply to dave_59:

Yes Dave. I can use the override by_instance.

Could you provide a small example with the adapter?, maybe i can find what i am doing wrong. I have tried several strings and it does not work.

6

In reply to JA:

Here you go. This is just the minimal amount of code to show factory object creation.

import uvm_pkg::*;
`include "uvm_macros.svh"
`define OBJ(x) \
`uvm_object_utils(x); \
function new(string name=`"x`"); super.new(name); endfunction

class trans extends uvm_sequence_item;
  `OBJ(trans)
  function void display;
    `uvm_info(get_name(),"display",UVM_LOW)
  endfunction
endclass
class trans_A extends trans;
  `OBJ(trans_A)
endclass
class trans_B extends trans;
  `OBJ(trans_B)
endclass
class adapter extends uvm_reg_adapter;
  `OBJ(adapter)
  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    trans item;
    item = trans::type_id::create(.contxt(get_name()));
    item.display();
    return item;
  endfunction
  virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
  endfunction
endclass
class mytest extends uvm_test;
  `uvm_component_utils(mytest);
  function new(string name="test",uvm_component parent);
    super.new(name,parent);
  endfunction
  adapter one,two;
  function void build_phase(uvm_phase phase);
    one = new("one");
    two = new("two");
    trans::type_id::set_inst_override(trans_A::get_type(), "one");
    trans::type_id::set_inst_override(trans_B::get_type(), "two");
    uvm_factory::get().print();
  endfunction
  task run_phase(uvm_phase phase);
    uvm_reg_bus_op 	rw;
    void'(one.reg2bus(rw));
    void'(two.reg2bus(rw));
  endtask
endclass

module top;
  initial run_test("mytest");
endmodule