How can i monitor if the assertion never ran in the testcase so that my testcase can fail

SystemVerilog
,
1

So I have written a property as shown below my question is how can I make my test fail if the assertion never started its ideal because I am trying to avoid the false pass, any suggestions?


module csr_sva(
input clk,clr,val;
);
bit sva_csr_en = 1;

property p_clear_reg_after_signal;
@(posedge clk) disable iff(~sva_csr_en)
$rose(clr) |-> ##1 (val == 0);
endproperty

assert_p_clear_reg : assert property(p_clear_reg_after_signal) $display(PASS); else `uvm_error(get_type_name, "FAIL");



class csr_hrd_self_clr extends base_test;
virtual task main_phase(uvm_phase phase);
write.reg

read.reg
endtask
endclass
2

In reply to Piyu:

To dynamically monitor if an assertion is ever triggered you can use the action block to modify variables, as shown below.


int pass, fail; 
assert_p_clear_reg : assert property(p_clear_reg_after_signal) pass=pass+1;
 else begin 
   fail=fail+1; 
   `uvm_error(get_type_name, "FAIL")
  end;
class csr_hrd_self

I believe that there might be some tool-dependent APIs to get statistics about the assertion results.

Ben Cohen
Ben@systemverilog.us
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Getting started with verification with SystemVerilog