How are race conditions betwen DUT and UVM are prevented?

chr_sue · August 31, 2018, 1:33pm

VHDL does not know problems like race conditions at all because of the tick-delay approach.
In my eyes the races are caused by the blocking and non-blocking assigments in Verilog/SystemVerilog. SV is adding re-active area in the scheduler. This minimizes also the appearance of races.
See the SV event scheduler (figure 4) in the paper I was referring.