In reply to chr_sue:
Thanks so far for the input. If the driver applies the values in a non-blocking way I would expect no race at all between monitor and driver. I am just concerned to read values from the monitor which are driven by the DUT based on the same event. Of course, adding a delay in reading the values of the DUT is possible but sounds a bit like a workaround. Its unclear to me why a language construct like the program is removed since it saves people from having these issues.
Could you explain how VHDL differs from Verilog DUTs regarding these race problematics?