In reply to chris_le:
It is not explained in a few words. In general it is caused by the Event Scheduler. SystemVerilog adds additional regions to the Verilog Event Scheduler to avoid the races and you can take care by clean coding. I found an interesting article by Cliff Cummings:
http://www.sunburst-design.com/papers/CummingsSNUG2006Boston_SystemVerilog_Events.pdf