Hierarchical path using array

SystemVerilog
, ,
2

You cannot use strings to create references to identifiers.
You can create list of class objects that refer to a hierarchical path, and put those objects in a list indexed by a string.

package probe_pkg;
  interface class abstract_probe;
    pure virtual function logic get_Rst;
  endclass
  abstract_probe list[string];
endpackage
  
interface probe #(string name) (input logic p);
  import probe_pkg::*;
  class concrete_probe implements abstract_probe;;
    function new(string name);
      list[name]=this;
    endfunction
    virtual function logic get_Rst();
      return p;
    endfunction
  endclass
  concrete_probe h=new(name);
endinterface

module top;
  
  dut dut();
  
  `define probe(path,name)  bind path.name probe#(`"name`") prb(Rst);
  
  `probe(dut,apb1)
  `probe(dut,ram1)
  `probe(dut,ram2)
  `probe(top,dut)
  
  initial foreach(probe_pkg::list[i])
    $display("%s.Rst is %b",i, probe_pkg::list[i].get_Rst());
endmodule

module dut;
  wire Rst=1;
  apb apb1();
  ram ram1();
  ram ram2();
endmodule

module apb;
  wire Rst=0;
endmodule
module ram;
  wire Rst;
endmodule

See my DVCon paper for more details on how this works.

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