Hi , i developed uvm tb for spi master core, when i am running tb with single test case , it was went up to master monitor and it is looping there it self due to forever in monitor run task,how to overcome this?

[chr_sue]

In reply to kathula venkatesh:

This is an indication something in your monitor is going wrong or it happens somewhere else. Could you please show how you assemble the transaction un the monitor
BTW, seq_items will not be constructed in the build_phase. . They do not belong to the topology of your testbench.