Help with SystemVerilog task to write AXIS stream to file

SystemVerilog
2

In reply to ianmurph:

By using # delays, you aren’t synchronizing tready with the interface clock, likely resulting in the values not being sampled correctly.

Try the following:


// Toggle the TREADY signal at random intervals to simulate back pressure:
fork
  forever @(posedge vntsc_resampler_if.clk) begin
    if (enable_random_delays == 1) begin
      random_interval = $urandom_range(0,5000); // number of clock cycles between forcing tready low
      random_delay = $urandom_range(0,200); // number of clock cycles to force tready low for
      vntsc_resampler_if.tready = 0;
      repeat (random_delay) @(posedge vntsc_resampler_if.clk);
      vntsc_resampler_if.tready = 1;
      repeat (random_interval) @(posedge vntsc_resampler_if.clk);
    end
  end
join_none