Hi mates,
I study computer science and therefore I want to look at SystemVerilog with QuestaSim cause I know VHDL/Verilog/SystemC very well.
My problem is I found a SV example on testbench.in (WWW.TESTBENCH.IN - Systemverilog for Verification) with all *.sv-files but they don’t compile without errors in QuestaSim.
The toplevels ‘monitor’, ‘driver’ and ‘environment’ don’t have access to the lower classes ‘scoreboard’ and ‘stimulus’.
Error message: Invalid type ‘xx’. Please check the type of the variable ‘xx’.
Maybe you guys could help me, I would be very grateful :)
There are a number of problems with this example. There are a few illegal constructs in the code, and there may be problems with the way you are compiling the code because the example does not use packages.
The interface declaration declares clk twice. Once as a port, and a second time internal to the interface. Verilog has two styles of port declarations: 1) an older style where you just list the names of ports in a list, and then you declare the port direction inside the module/interface, and a third time inside to declare its type. 2) A newer stle (called ANSI) where you declare the port direction, type, and name inside the port list. You cannot mix the two styles.
Another problem is that the the driver class is trying to make procedural assignments to the wires in the interface. That is illegal, you can only make procedural assignments to variables. See What's the deal with those wire’s and reg’s in Verilog - Verification Horizons So the interface should look like
interface intf_cnt(input clk);
logic reset;
logic data;
logic [0:3] count;
endinterface
There is also a problem with the way the environment class is constructed in the test. The constructor contains a fork/join_none block that spawns a thread and the constructor is called as part of a static initialization declaration. That is illegal because you can only spawn threads from threads created by initial or always blocks. So you need to remove the static initialization (a good rule to follow in any case because of potential races between static initializations) and call the constructor inside the initial block.
program testcase(intf_cnt intf);
environment env; // = new(intf);
initial
begin
env =new(intf);
Finally, SystemVerilog has the concept of compilation units. When you compile a class in a separately from another class, is no data type visibility between the two compilations unless you use a package. So you must compile this example as one concatenated file, or one file that `includes all the other files. Some simulators treat all files on a single command line as if they were written as a single file, but Questa does not do that by default.