In reply to ben@SystemVerilog.us:
I am quite confused with your UVM example.
Maybe let me rephrase my question to a simple test case below:
What assert(logic) could be used for the following always @(*) block ?
module test_assert
(
input clk,
output done
);
// a list of 8 integers
localparam MAX_VALUE = 10;
localparam NUM_OF_ITEMS = 8;
reg [$clog2(MAX_VALUE)-1:0] number_list [NUM_OF_ITEMS-1:0];
generate
genvar list_index;
for(list_index=0; list_index<NUM_OF_ITEMS; list_index=list_index+1)
begin: assign_number_to_list
always @(posedge clk)
number_list[list_index] <= list_index; // a list that contains {1,2,3,4,5,6,7,8}
end
endgenerate
// we have 2,4,6 as even integer
// we have 1,3,5,7 as odd integer
reg [$clog2(NUM_OF_ITEMS)-1:0] num_of_evens_minus_num_of_odds;
integer index;
always @(*)
begin
num_of_evens_minus_num_of_odds <= 0;
for(index=0; index<NUM_OF_ITEMS; index=index+1)
begin: computation_logic
if((number_list[index] % 2) == 0) // even integer
num_of_evens_minus_num_of_odds <= num_of_evens_minus_num_of_odds + 1;
else num_of_evens_minus_num_of_odds <= num_of_evens_minus_num_of_odds - 1;
end
end
always @(posedge clk) done <= 1; // the always @(*) will finish in 1 clock cycle
endmodule