Help - QuestaSim can't randomize for array of union

SystemVerilog
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2

In reply to xdarksadx:

It would help to show a complete runnable example. This worked for me

module top;
  typedef union packed {
    bit [31:0] b,c;
  }prot_slot_u ;
  typedef struct packed {
    bit [15:0] a,b;
  } ctl_slot_s;
  
  typedef union packed {
    bit [3:0][7:0] rawdata;
    prot_slot_u prot; // another union
    ctl_slot_s  ctl;  // this is packed struct 
} my_slot_u;

my_slot_u [3:0] slot;
  
  initial begin
    assert(std::randomize(slot));
    $displayh("%p", slot);
  end
endmodule