Help on using preprocessor directives

SystemVerilog
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1

I need to create a directed test. My plan is to let the user choose how many commands he wants to generate, and for each command he has the option to set the values. So I’m thinking to create an include file where the designer can set the values he wants.

This is the content of the include file:


`define ITEMS      // Set the number of items you want
`define CMD        // Type of command you want. 1-WRITE 0-READ
`define ADDR       // Address
`define DATA       // Data to be written
`define TD         // Read frame Delay
`define ADDR_INC   // Read address increment
`define N          // Number of reads

Then this is my code to generate each command:


repeat(`ITEMS) begin
  if(`CMD) begin
    wr_seq.send_cmd_seq.pkt.addr = `ADDR;
    wr_seq.send_cmd_seq.pkt.data = `DATA;
    wr_seq.start(m_sequencer);
  end
  else begin
    rd_seq.send_cmd_seq.pkt.addr     = `ADDR;
    rd_seq.send_cmd_seq.pkt.td       = `TD;
    rd_seq.send_cmd_seq.pkt.addr_inc = `ADDR_INC;
    rd_seq.send_cmd_seq.pkt.num_rd   = `N;
    rd_seq.start(m_sequencer);
  end
end

Now my problem is that code will have the same values for different items. I’m looking for a way that the user can change different values for different items.

2

I would recommend using the plusargs feature of SystemVerilog instead of a file of `define statements. This gives you complete flexibility at runtime while eliminating the need for you to recompile for every test.

You can create a pre-defined file of the plusargs and specify it on the simulation command line with the -f option.

3

In reply to cgales:

I think its better to create a packet and use randomization to create data randomly.

In your case the repeat will repeat same sequence again and again. So either use packet based randomization or scope variable randomization or system functions to randomize.