Help me resolve Bad handle or ref erro

SystemVerilog
1

When i simulate this snip pate of code iam getting below mentioned errors,Please help me resolve this.

Here my intention is randomizing a variable and priniting that.

class A;
rand int a;
constraint c {a>=1;a<=10;}
endclass
module Rand_ex;
A A_inst;
initial begin
$display(“a=%d”,A_inst.a);
end

endmodule:Rand_ex

Simulation log:

Loading sv_std.std

Loading work.rand_Ex_sv_unit

Loading work.Rand_ex(fast)

run -all

** Fatal: (SIGSEGV) Bad handle or reference.

Time: 0 ns Iteration: 0 Process: /Rand_ex File: rand_Ex.sv

** Fatal: (vsim-8324) Parameter 2 is bad. This may involve a null ref handle.

Time: 0 ns Iteration: 0 Process: /Rand_ex/#INITIAL#7 File: rand_Ex.sv

Fatal error at rand_Ex.sv line 8

HDL call sequence:

Stopped at rand_Ex.sv 8

quit -f

2

You need to construct an object before you can reference it. A_inst is a class variable, not an instance (object) of a class.

initial begin
    A_inst = new();
    $display("a=%d",A_inst.a);
  end