Hello World+System Verilog

SystemVerilog
1

Guys

I wrote some small piece of code and mistyped “display” and i could see the compile went through

There are 2 things here
i)No syntax error which i expect to see
ii)I don’t expect the simulator to compile the next N lines of code.

  1. Am not sure if am missing something, can someone help here?

3)Link Syntax error? - EDA Playground

-Best Regards
Hash

2

Hi Hash,

The output for the above code is

Loading sv_std.std

Loading work.subashb

[b]# ** Warning: (vsim-PLI-3003) design.sv(6): [TOFD] - System task or function ‘$dsiplay’ is not defined

Region: /subashb

onElabError resume

resume

run -all

******************

******************

\\\\\aaaaaaa

exit

For your code, This simulator is giving warning and next if you see there is OneLabError Resume. So seems compiler is giving warning for the wrongly spelled display and not printing that display statement.Rest all, display statements are getting executed.

Not sure of the tool much EDA Playground that you are using. May be because of that it just points with OneLabError and then resumes as the log saying. Check with other tools.

Regards,
Ankita

3

The reason you are getting a run-time warning and not a compilation error is because it is a ‘$’ call which is used to identify a system task or function (as the warning indicates). While ‘display' is a pre-defined Verilog function, the '’ notation is also used to identify user PLI calls which are resolved at run-time, hence there is no compilation error.

Since your ‘$dsiplay’ function isn’t registered at run-time, the warning is generated and the function is treated as a null function.

4

Thanks Ankita/cgales

But am not very sure if there any way to make ModelSim fail during compile or during run time instead of simply giving a warning?

-Best Regards
Hash

5

In reply to Hash:

vsim -fatal 3003