Having problem with FOR LOOP which leads to endless loop in system verilog

[uvm_novice]

In reply to deepak_sadasivam_uvm:

for(int ii = num_q.size(); ii >= 0; ii--)begin - remove 'd it will work
Issue is 'd0 - It is treating as unsigned integer 32'd0
ii will become 32'hffff_ffff after 0 and it is greater than 0