Having problem with FOR LOOP which leads to endless loop in system verilog

SystemVerilog
3

In reply to kddholak:

Hi,

Thanks for answering but my question is more understand the below code:

Working code:

for(int ii = num_q.size(); ii > 'd0; ii--)begin
  $display("Loop count=%0d",ii);
  if(num_q[ii-1] inside del_q)
    num_q.delete(ii-1);
  else
   continue;
end

Code which goes to infinite loop:

for(int ii = num_q.size(); ii >= 'd0; ii--)begin
  $display("Loop count=%0d",ii);
  if(num_q[ii-1] inside del_q)
    num_q.delete(ii-1);
  else
   continue;
end

can you help here what going wrong.